SH7721 datasheet(158/1524 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev. 3.00 Jan. 18, 2008 Page 96 of 1458

REJ09B0033-0300

Table 3.7

DSP Mode Extended System Control Instructions

Instruction

Operation

Number of

Execution States

STC RS, Rn

→Rn

STC RE, Rn

→Rn

STC.L RS, @-Rn

Rn-4

→Rn, RS→(Rn)

STC.L RE, @-Rn

Rn-4

→Rn, RE→(Rn)

LDC.L @Rn+, RS

(Rn)

→RS, Rn+4→Rn

LDC.L @Rn+, RE

(Rn)

→RE, Rn+4→Rn

LDC Rn,RS

→RS

LDC Rn, RE

→RE

(3)

Restrictions on Repeat Loop Control

(a)

Repeat control instruction assignment

The SETRC instruction must be executed after executing the LDRS and LDRE instructions. In

addition, note that at least one instruction is required between the SETRC instruction and a repeat

start instruction.

(b)

Illegal instruction one or more instructions following the repeat detection instruction

If one of the following instructions is executed between an instruction following a repeat detection

instruction to a repeat end instruction, an illegal instruction exception occurs.

• Branch instructions

BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA

• Repeat control instructions

SETRC, LDRS, LDRE

• Load instructions for SR, RS, and RE registers

LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS

Note:

This restriction applies to all instructions for a repeat loop consisting of one to three

instructions and to three instructions including a repeat end instruction.

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