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150 / 1524 page  Section 3 DSP Operating Unit Rev. 3.00 Jan. 18, 2008 Page 88 of 1458 REJ09B0033-0300 Before entering the exception handling state, all bits including the DSP extension bits of the SR registers are saved in the SSR. Before returning from the exception handling, all bits including the DSP extension bits of the SR must be restored. If the repeat control must be recovered before entering the exception handling state, the RS and RE registers must be recovered to the value that existed before exception handling. In addition, if it is necessary to recover modulo control before entering the exception handling state, the MOD register must be recovered to the value that existed before exception handling. 3.2.4 DSP Registers The DSP unit incorporates eight data registers (A0, A1, X0, X1, Y0, Y1, M0, and M1) and a status register (DSR). Figure 3.3 shows the DSP register configuration. These are 32-bit width registers with the exception of registers A0 and A1. Registers A0 and A1 include 8 guard bits (fields A0G and A1G), giving them a total width of 40 bits. The DSR register stores the DSP data operation result (zero, negative, others). The DSP register has a DC bit whose function is similar to the T bit in the CPU register. For details on DSR bits, refer to section 3.5, DSP Data Operation Instructions. 39 A0G A1G A0 A1 M0 M1 X0 X1 Y0 Y1 ................ GT V N Z CS[2:0] DC (a) DSP data registers (b) DSP status register (DSR) 32 31 0 31 8 765 4 3 1 0 Initial value DSR : All 0 Others: Undefined Figure 3.3 DSP Register Configuration |
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