SH7721 datasheet(481/1524 Pages) RENESAS

481 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 419 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

R/(W)* Address Error Flag

Indicates that an address error occurred during DMA

transfer. If this bit is set, DMA transfer is disabled even if

the DE bit in CHCR and the DME bit in DMAOR are set to

1. This bit can only be cleared by writing 0 after reading

0: No DMAC address error

[Clearing condition]

Writing AE = 0 after AE = 1 read

1: DMAC address error occurs

NMIF

R/(W)* NMI Flag

Indicates that an NMI interrupt occurred. If this bit is set,

DMA transfer is disabled even if the DE bit in CHCR and

the DME bit in DMAOR are set to 1. This bit can only be

cleared by writing 0 after reading 1.

When the NMI is input, the DMA transfer in progress can

be done in one transfer unit. When the DMAC is not in

operational, the NMIF bit is set to 1 even if the NMI

interrupt was input.

0: No NMI interrupt

[Clearing condition]

Writing NMIF = 0 after NMIF = 1 read

1: NMI interrupt occurs

DME

R/W

DMA Master Enable

Enables or disables DMA transfers on all channels. If the

DME bit and the DE bit in CHCR are set to 1, transfer is

enabled. In this time, all of the bits TE in CHCR, NMIF,

and AE in DMAOR must be 0. If this bit is cleared during

transfer, transfers in all channels are terminated.

0: Disables DMA transfers on all channels

1: Enables DMA transfers on all channels

Note:

Writing 0 is possible to clear the flag.

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