SH7721 datasheet(456/1524 Pages) RENESAS

tên linh kiện	SH7721

Giải thích chi tiết về linh kiện	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 394 of 1458

REJ09B0033-0300

(1)

Basic Timing for Memory Card Interface

Figure 9.38 shows the basic timing of the PCMCIA IC memory card interface. If areas 5 and 6 in

the physical space are specified as the PCMCIA interface, accessing the common memory areas in

areas 5 and 6 automatically accesses the IC memory card interface. If the external bus frequency

(CKIO) increases, the setup times and hold times for the address pins (A25 to A0) to RD and WE,

card enable signals (

CE1A, CE2A, CE1B, CE2B), and write data (D15 to D0) become

insufficient. To prevent this error, the LSI can specify the setup times and hold times for areas 5

and 6 in the physical space independently, using CS5BWCR and CS6BWCR. In the PCMCIA

interface, as in the normal space interface, a software wait or hardware wait can be inserted using

the WAIT pin. Figure 9.39 shows the PCMCIA memory bus wait timing.

Tpcm1w

CKIO

A25 to A0

CExx

RD/

D15 to D0

Read

Write

Tpcm2

Tpcm1

Tpcm1w

Figure 9.38

Basic Access Timing for PCMCIA Memory Card Interface

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