SH7721 datasheet(447/1524 Pages) RENESAS

447 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 385 of 1458

REJ09B0033-0300

CKIO

CKE

A25 to A0

CSn

RD/

RAS

DQMxx

D31 to D0

Tpw

DACKn*2

Tdpd

A12/A11*1

CAS

1. Address pin to be connected to the A10 pin of SDRAM.

2. The waveform for DACKn is when active low is specified.

Trc

Hi-Z

Trc

Notes:

Figure 9.30

Transition Timing in Deep Power-Down Mode

9.5.6

Burst ROM (Clock Asynchronous) Interface

The burst ROM (clock asynchronous) interface is used to access a memory with a high-speed read

function using a method of address switching called the burst mode or page mode. In a burst ROM

(clock asynchronous) interface, basically the same access as the normal space is performed, but

the 2nd and subsequent accesses are performed only by changing the address, without negating the

RD signal at the end of the 1st cycle. In the 2nd and subsequent accesses, addresses are changed at

the falling edge of the CKIO.

For the 1st access cycle, the number of wait cycles specified by the W[3:0] bits in CSnWCR is

inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the

BW[1:0] bits in CSnWCR is inserted.

In the access to the burst ROM (clock asynchronous), the

BS signal is asserted only to the first

access cycle. An external wait input is valid only to the first access cycle.

In the single access or write access that do not perform the burst operation in the burst ROM

(clock asynchronous) interface, access timing is same as a normal space.

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