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SH7721 bảng dữ liệu(PDF) 439 Page - Renesas Technology Corp

tên linh kiện SH7721
Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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SH7721 bảng dữ liệu(HTML) 439 Page - Renesas Technology Corp

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Section 9
Bus State Controller (BSC)
Rev. 3.00 Jan. 18, 2008 Page 377 of 1458
REJ09B0033-0300
(9)
Relationship between Refresh Requests and Bus Cycles
If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle
to be completed. If a refresh request occurs while the bus is released by the bus arbitration
function, the refresh will not be executed until the bus mastership is acquired. This LSI supports
requests by the
REFOUT pin for the bus mastership while waiting for the refresh request. The
REFOUT pin is asserted low until the bus mastership is acquired.
If a new refresh request occurs while waiting for the previous refresh request, the previous refresh
request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus
mastership occupation must be prevented from occurring.
If a bus mastership is requested during self-refresh, the bus will not be released until the self-
refresh is completed.



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