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SH7721 bảng dữ liệu(PDF) 375 Page - Renesas Technology Corp |
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SH7721 bảng dữ liệu(HTML) 375 Page - Renesas Technology Corp |
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375 / 1524 page ![]() Section 9 Bus State Controller (BSC) Rev. 3.00 Jan. 18, 2008 Page 313 of 1458 REJ09B0033-0300 Bit Bit Name Initial Value R/W Description 6 WM 0 R/W External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait is valid 1: External wait is ignored 5 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. • CS4WCR Bit Bit Name Initial Value R/W Description 31 to 21 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 20 BEN 0 R/W Burst Enable Specification Enables or disables 8-burst access for a 16-bit bus width or 16- burst access for an 8-bit bus width during 16-byte access. If this bit is set to 1, 2-burst access is performed four times when the bus width is 16 bits and 4-burst access is performed four times when the bus width is 8 bits. To use a device that does not support 8-burst access or 16- burst access, set this bit to 1. 0: Enables 8-burst access for a 16-bit bus width and 16-burst access for an 8-bit bus width. 1: Disables 8-burst access for a 16-bit bus width and 16-burst access for an 8-bit bus width. 19, 18 All 0 R Reserved These bits are always read as 0. The write value should always be 0. |
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