SH7721 datasheet(361/1524 Pages) RENESAS

361 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 299 of 1458

REJ09B0033-0300

9.4.3

CSn Space Wait Control Register (CSnWCR)

This register specifies various wait cycles for memory accesses. The bit configuration of this

TYPE0) specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before

accessing the target area. Specify CSnBCR first, then specify CSnWCR.

(n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)

(1)

Normal Space, Byte-Selection SRAM

• CS0WCR, CS6BWCR

Bit

Bit Name

Initial

Value

R/W

Description

31 to 21



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

BAS

R/W

Byte Access Selection for Byte-Selection SRAM

Specifies the

WEn (BEn) and RD/WR signal timing when

the byte-selection SRAM interface is used.

0: Asserts the

WEn (BEn) signal at the read/write timing

and asserts the RD/

WR signal during the write access

cycle.

1: Asserts the

WEn (BEn) signal during the read/write

access cycle and asserts the RD/

WR signal at the write

timing.

19 to 13



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

SW1

SW0

R/W

Number of Delay Cycles from Address,

CSn Assertion to

RD, WEn (BEn) Assertion

Specify the number of delay cycles from address and

CSn

assertion to

RD and WEn (BEn) assertion.

00: 0.5 cycle

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

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