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SH7713 bảng dữ liệu(PDF) 279 Page - Renesas Technology Corp

tên linh kiện SH7713
Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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Section 8 Interrupt Controller (INTC)
Rev.1.50 Aug. 30, 2006 Page 239 of 860
REJ09B0288-0150
The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by the IRL interrupt
handling.
Priority
encoder
Interrupt
request
IRL3 to IRL0
IRL3 to IRL0
4
SH7713
Figure 8.2 Example of IRL Interrupt Connection
8.3.4
On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following 13 modules:
• Direct memory access controller (DMAC)
• Serial communication interface with FIFO (SCIF0 and SCIF1)
• Direct memory access controller for ethernet controller (E-DMAC)
(includes an EtherC interrupt)
• Serial I/O with FIFO (SIOF0 and SIOF1)
• Timer unit (TMU0 to TMU2)
• Realtime clock (RTC)
• Watchdog timer (WDT)
• Bus state controller (BSC)
• User-debugging interface (H-UDI)
Not every interrupt source is assigned a different interrupt vector. Sources are reflected in the
interrupt event registers (INTEVT and INTEVT2). It is easy to identify sources by using the value
of INTEVT or INTEVT2 as a branch offset.
A priority level (from 0 to 15) can be set for each module except the H-UDI by writing to the
interrupt priority registers A, B, and E to I (IPRA, IPRB, and IPRE to IPRI). The priority level of
the H-UDI interrupt is 15 (fixed).



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