SH7713 datasheet(277/904 Pages) RENESAS

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Section 8 Interrupt Controller (INTC)

Rev.1.50 Aug. 30, 2006 Page 237 of 860

REJ09B0288-0150

8.2

Input/Output Pins

Table 8.1 shows the INTC pin configuration.

Table 8.1

Pin Configuration

Name

Abbreviation

I/O

Description

Nonmaskable interrupt input pin

NMI

Input

Input of interrupt request signal, not

maskable by the interrupt mask bits

in SR

Interrupt input pins

IRQ5 to IRQ0

IRL3 to IRL0*1

Input

Input of interrupt request signals

Bus mastership request output

pin*

IRQOUT

Output

Notifies that an interrupt request

has generated

Notes: 1. The

IRL3 to IRL0 pins and the IRQ3 to IRQ0 cannot be used simultaneously because

these pins are multiplexed with the IRQ3 to IRQ0 pins.

2. When the NMI or H-UDI interrupt requests are generated and the response time of the

CPU is short, this pin may not be asserted.

8.3

Interrupt Sources

There are four types of interrupt sources: NMI, IRQ, IRL, and on-chip peripheral modules. Each

interrupt has a priority level (0 to 16), with 1 the lowest and 16 the highest. Priority level 0 masks

an interrupt, so the interrupt request is ignored.

8.3.1

NMI Interrupt

The NMI interrupt has the highest priority level of 16. When the BLMSK bit in the interrupt

control register 1 (ICR1) is set to 1 or the BL bit in the status register (SR) is 0 and the MAI bit in

ICR1 is 0, NMI interrupts are accepted. NMI interrupts are edge-detected. In sleep or standby

mode, the interrupt is accepted regardless of the BL setting. The NMI edge select bit (NMIE) in

the interrupt control register 0 (ICR0) is used to select either rising or falling edge detection.

When using edge-input detection for NMI interrupts, a pulse width of at least two P

φ cycles

(peripheral clock) is necessary. NMI interrupt exception handling does not affect the interrupt

mask level bits (I3 to I0) in the status register (SR). When the BL bit is 1 and the BLMSK bit in

ICR1 is set to 1, only the NMI interrupt is accepted.

It is possible to wake the chip up from sleep mode or standby mode with the NMI interrupt.

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