SH7713 datasheet(205/904 Pages) RENESAS

205 / 904 page

Section 4 Exception Handling

Rev.1.50 Aug. 30, 2006 Page 165 of 860

REJ09B0288-0150

4.3

Individual Exception Operations

This section describes the conditions for specific exception handling, and the processor operations.

Resets and general exceptions are described in particular. For details on interrupt operations, refer

to section 8, Interrupt Controller (INTC).

4.3.1

Resets

Power-On Reset:

• Conditions

Power-on reset is request

• Operations

Set EXPEVT to H'000, initialize the CPU and on-chip peripheral modules, and branch to the

reset vector H

′A0000000. For details, refer to the register descriptions in the relevant sections.

Be sure to perform power-On Reset at the time of a power supply injection.

Manual Reset:

• Conditions

Manual reset is request

• Operations

Set EXPEVT to H'020, initialize the CPU and on-chip peripheral modules, and branch to the

reset vector H

′A0000000. For details, refer to the register descriptions in the relevant sections.

H-UDI Reset:

• Conditions

An H-UDI reset command is input (see section 22.4.4, H-UDI Reset.)

• Operations

EXPEVT is set to H'000, vector base register (VBR) and status register (SR) are initialized,

and branched to the reset vector (H'A0000000). VBR is cleared to H'00000000 by

initialization. In SR, the MD, RB, and BL bits are set to 1, the DSP bit is cleared to 0, and the

interrupt mask bits (I3 to I0) are set to B'1111. Then, the CPU and on-chip peripheral modules

are initialized. For details, see the Register Description in each section.

SH7713 bảng dữ liệu(PDF) 205 Page - Renesas Technology Corp