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SH7713 bảng dữ liệu(PDF) 195 Page - Renesas Technology Corp |
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SH7713 bảng dữ liệu(HTML) 195 Page - Renesas Technology Corp |
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195 / 904 page ![]() Section 4 Exception Handling Rev.1.50 Aug. 30, 2006 Page 155 of 860 REJ09B0288-0150 Section 4 Exception Handling Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. For example, if an attempt is made to execute an undefined instruction code or an instruction protected by the CPU processing mode, a control function may be required to return to the source program by executing the appropriate operation or to report an abnormality and carry out end processing. In addition, a function to control processing requested by LSI on-chip modules or an LSI external module to the CPU may also be required. Transferring control to a user-defined exception processing routine and executing the process to support the above functions are called exception handling. This LSI has two types of exceptions: general exceptions and interrupts. The user can execute the required processing by assigning exception handling routines corresponding to the required exception processing and then return to the source program. A reset input can terminate the normal program execution and pass control to the reset vector after register initialization. This reset operation can also be regarded as an exception handling. This section describes an overview of the exception handling operation. Here, general exceptions and interrupts are referred to as exception handling. For interrupts, this section describes only the process executed for interrupt requests. For details on how to generate an interrupt request, refer to section 8, Interrupt Controller (INTC). 4.1 Register Descriptions There are five registers for exception handling. A register with an undefined initial value should be initialized by the software. Refer to section 23, List of Registers, for the addresses and access sizes of these registers. • TRAPA exception register (TRA) • Exception event register (EXPEVT) • Interrupt event register (INTEVT) • Interrupt event register 2 (INTEVT2) • Exception address register (TEA) |
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