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SH7713 bảng dữ liệu(PDF) 411 Page - Renesas Technology Corp

tên linh kiện SH7713
Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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Section 12 Bus State Controller (BSC)
Rev.1.50 Aug. 30, 2006 Page 371 of 860
REJ09B0288-0150
Bit
Bit Name
Initial
Value
R/W
Description
4
3
TRWL1
TRWL0
0
0
R/W
R/W
Number of Wait Cycles Waiting Start of Precharge
Specify the number of minimum wait cycles to be inserted
to wait the start of precharge. The setting for areas 2 and 3
is common.
(1) This LSI is in non-bank active mode from the issue of
the WRITA command to the start of auto-precharge in
SDRAM, and issues the ACTV command for the same
bank after issuing the WRITA command.
Confirm how many cycles are required from the
reception of the WRITA command to the start of auto-
precharge in each SDRAM data sheet.
Set this bit so that the number of cycles is not above the
cycles specified by this bit.
(2) This LSI is in bank active mode from issuing the WRIT
command to issuing the PRE command, and the access
to different row address in the same bank is performed.
00: 0 cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
2
0
R
Reserved
This bit is always read as 0. The write value should always
be 0.



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