SH7713 datasheet(367/904 Pages) RENESAS

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Section 11 On-Chip Oscillation Circuits

Rev.1.50 Aug. 30, 2006 Page 327 of 860

REJ09B0288-0150

H'5A

Write data

Address: H'A415FF84

WTCNT write

H'A5

Write data

Address: H'A415FF86

WTCSR write

Figure 11.3 Writing to WTCNT and WTCSR

11.8

Using WDT

11.8.1

Canceling Standbys

The WDT can be used to cancel standby mode with an interrupt such as an NMI. The procedure is

described below. (The WDT does not run when resets are used for canceling, so keep the

RESETP

RESETM pin low until the clock stabilizes.)

1. Before transitioning to standby mode, always clear the TME bit in WTCSR to 0. When the

TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count

overflows.

2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for

the counter in WTCNT. These values should ensure that the time till count overflow is longer

than the clock oscillation settling time.

3. Move to standby mode by executing a SLEEP instruction to stop the clock.

4. The WDT starts counting by detecting the edge change of the NMI signal.

5. When the WDT count overflows, the CPG starts supplying the clock and the processor

resumes operation. The WOVF flag in WTCSR is not set at this time.

6. Since the WDT continues counting from H'00, clear the STBY bit in STBCR to 0 in the

interrupt processing program and this will stop the WDT. When the STBY bit remains 1, the

LSI again enters the standby mode when the WDT has counted up to H'80. This standby mode

can be canceled by power-on resets.

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