SH7708 datasheet(231/633 Pages) RENESAS

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Bit 1—Refresh Mode (RMODE): Selects whether to perform an ordinary refresh or a self-refresh

when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 0, a CAS-before-RAS refresh or an

auto-refresh is performed on DRAM, synchronous DRAM or pseudo-SRAM at the period set by

the refresh-related registers RTCNT, RTCOR and RTCSR. When a refresh request occurs during

an external bus cycle, the bus cycle will be ended and the refresh cycle performed. When the

RFSH bit is 1 and this bit is also 1, the DRAM, synchronous DRAM or pseudo-SRAM will wait

for the end of any executing external bus cycle before going into a self-refresh. All refresh

requests to memory that is in the self-refresh state are ignored.

Bit 1: RMODE

Description

CAS-before-RAS refresh (RFSH must be 1)

(Initial value)

Self-refresh (RFSH must be 1)

Bit 0— Extended Data Out (EDOMODE): Specifies the timing of data sampling during data reads

when using DRAM in EDO mode. Operating timing of memory other than DRAM does not

change even if this bit is set. This bit is valid only for DRAM connected to area 3. Do not set this

bit to 1 when using synchronous DRAM or pseudo-SRAM.

Bit 0: EDOMODE

Description

Set when using normal DRAM. Data is sampled during read cycle on the

falling edge of CKIO.

(Initial value)

Set when using EDO mode DRAM. Data is sampled during read cycle on the

rising edge of CKIO. Also, RAS signal negation is delayed 1/2 a CKIO

machine cycle.

SH7708 bảng dữ liệu(PDF) 231 Page - Renesas Technology Corp