SH7708 datasheet(160/633 Pages) RENESAS

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142

Table 8.1

Power-Down Modes

State

Mode

Transition

Conditions

CPG

CPU

Reg-

ister

On-Chip

Memory

On-Chip

Peripheral

Modules

Pins

External

Memory

Canceling

Procedure

Sleep

mode

Execute SLEEP

instruction with

STBY bit cleared

to 0 in STBCR

Runs Halts

(Reg-

ister

held)

Held

Run

Held Refresh

1. Interrupt

2. Reset

Standby

mode

Execute SLEEP

instruction with

STBY bit set to 1

in STBCR

Halts Halts

(Reg-

ister

held)

Held

Halts*

Held Self-

refresh

1. Interrupt

2. Reset

Hardware

standby

mode

Drive CA pin

low

Halts Halts

(Reg-

ister

held)

Held

Halts*

Held Self-

refresh

Power-on

reset

Module

standby

Set MSTP bit of

STBCR to 1

Runs Runs

Held

Specified

module

halts

Refresh

1. Clear

MSTP

bit to 0

2. Reset

Notes: 1. The RTC still runs if the START bit in RCR2 is set to 1 (see section 12, Realtime Clock

(RTC)). TMU still runs when output of the RTC is used as input to its counter (see

section 11, Timer (TMU)).

2. Depends on the on-chip supporting module.

TMU external pin: Held

SCI external pin: Reset

3. The RTC still runs if the START bit in RCR2 is set to 1 (see section 12, Realtime Clock

(RTC)). The TMU does not run.

8.1.2

Table 8.2 shows the configuration of the control register for the power-down modes.

Table 8.2

Name

Abbreviation

R/W

Initial Value

Address

Access Size

Standby control register

STBCR

R/W

H'00*

H'FFFFFF82

Byte

Note: * Initialized by a power-on reset. In a manual reset, the register contents are retained.

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