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SH7708 bảng dữ liệu(PDF) 128 Page - Renesas Technology Corp

tên linh kiện SH7708
Giải thích chi tiết về linh kiện  SuperH??RISC engine
PDF  633 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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SH7708 bảng dữ liệu(HTML) 128 Page - Renesas Technology Corp

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6.2.1
NMI Interrupts
The NMI interrupt has the highest priority level of 16. It is always accepted unless the BL bit in
the status register in the CPU is set to 1, and is edge-detected. In sleep or standby mode, the
interrupt is accepted regardless of the BL setting. The NMI edge select bit (NMIE) in the interrupt
control register (ICR) is used to select either the rising or falling edge. When the NMIE bit in the
ICR register is changed, the NMI interrupt is not detected for 20 cycles after changing ICR. NMI
interrupt exception handling does not affect the interrupt mask level bits (I3–I0) in the status
register (SR).
6.2.2
IRL Interrupts
IRL interrupts are input by level at pins
IRL3–IRL0. The priority level is the level indicated by
pins
IRL3–IRL0. An IRL3–IRL0 value of 0 (0000) indicates the highest-level interrupt request
(interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority
level 0). Figure 6.2 shows an examples of an IRL interrupt connection. Table 6.3 shows
IRL pins
and interrupt levels.
Interrupt
request
Priority
encoder
IRL3 to IRL0
4
SH7708Series
IRL3 to IRL0
Figure 6.2 Example of IRL Interrupt Connection



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