SH7708 datasheet(409/633 Pages) RENESAS

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In receiving, the SCI operates as follows:

1. The SCI synchronizes with serial clock input or output and initializes internally.

2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the

data, the SCI checks that RDRF is 0 so that receive data can be loaded from SCRSR into

SCRDR. If this check is passed, the SCI sets RDRF to 1 and stores the received data in

SCRDR. If the check is not passed (receive error), the SCI operates as indicated in table 13.12.

This state prevents further transmission or reception. While receiving, the RDRF bit is not set

to 1. Be sure to clear the error flag.

3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR,

the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receive-

data-full interrupt enable bit (RIE) in SCSCR is also set to 1, the SCI requests a receive-error

interrupt (ERI).

Figure 13.19 shows an example of the SCI receive operation.

Bit 7

Bit 0

Bit 7

Bit 0

Bit 1

Bit 6

Serial clock

Serial

data

Transfer direction

Bit 7

RXI interrupt handler

reads data and

clears RDRF

bit to 0

1 frame

RXI interrupt

request

RXI interrupt

request

ERI interrupt

request generated

by overrun error

RDRF

ORER

Figure 13.19 Example of SCI Receive Operation

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