M16CSLASH26 datasheet(139/239 Pages) RENESAS

139 / 239 page

Renesas Technology Corp.

Clock Asynchronous Serial I/O (UART) Mode

133

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)

• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)

Figure 1.15.19. Typical transmit timing in UART mode (UART0, UART1)

fi : frequency of BRGi count source (f1SIO, f2SIO, f8SIO, f32SIO)

Transmit enable

bit(TE)

Transmit buffer

empty flag(TI)

Transmit register

empty flag (TXEPT)

Start

bit

Parity

bit

TxDi

CTSi

The above timing applies to the following settings :

* Parity is enabled.

* One stop bit.

* CTS function is selected.

* Transmit interrupt cause select bit = 1 .

Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT

fEXT : frequency of BRGi count source (external clock)

n : value set to BRGi

Transmit interrupt

request bit (IR)

Cleared to 0 when interrupt request is accepted, or cleared by software

Transmit enable

bit(TE)

Transmit buffer

empty flag(TI)

TxDi

Transmit register

empty flag (TXEPT)

The above timing applies to the following settings :

* Parity is disabled.

* Two stop bits.

* CTS function is disabled.

* Transmit interrupt cause select bit = 0 .

Transfer clock

Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT

fEXT : frequency of BRGi count source (external clock)

n : value set to BRGi

Transmit interrupt

request bit (IR)

Shown in ( ) are bit symbols.

Transfer clock

D0 D1

D2 D3 D4 D5 D6 D7

D0 D1 D2 D3

D4 D5 D6

D0 D1

Stopped pulsing because transmit enable bit = 0

Stop

bit

Transferred from UARTi transmit buffer register to UARTi transmit register

Start

bit

The transfer clock stops momentarily as CTS is H when the stop bit is checked.

The transfer clock starts as the transfer starts immediately CTS changes to L .

Data is set in UARTi transmit buffer register

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1

SPSP

Transferred from UARTi transmit buffer register to UARTi transmit register

Stop

bit

Stop

bit

Data is set in UARTi transmit buffer register.

Cleared to 0 when interrupt request is accepted, or cleared by software

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