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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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R8C/15 bảng dữ liệu(PDF) 188 Page - Renesas Technology Corp |
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R8C/15 bảng dữ liệu(HTML) 188 Page - Renesas Technology Corp |
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188 / 277 page  R8C/14 Group, R8C/15 Group 16. A/D Converter Rev.2.10 Jan 19, 2006 Page 176 of 253 REJ09B0164-0210 16.3 Sample and Hold When the SMP bit in the ADCON2 register is set to “1” (with sample and hold function), A/D conversion rate per pin increases to 28 φAD cycles for 8-bit resolution or 33φAD cycles for 10-bit resolution. The sample and hold function is available in all operating modes. Start the A/D conversion after selecting whether the sample and hold circuit is to be used or not. When performing the A/D conversion, charge the comparator capacitor in the microcomputer. Figure 16.6 shows the Timing Diagram of A/D Conversion. Figure 16.6 Timing Diagram of A/D Conversion 16.4 A/D Conversion Cycles Figure 16.7 shows the A/D Conversion Cycles. Figure 16.7 A/D Conversion Cycles Sampling Time 4ø AD cycle Sample & Hold Disabled Conversion time at the 1st bit at the 2nd bit Comparison Time Sampling Time 2.5ø AD cycle Comparison Time Sampling Time 2.5ø AD cycle Comparison Time * Repeat until conversion ends Sampling Time 4ø AD cycle Sample & Hold Enabled Conversion time at the 1st bit at the 2nd bit Comparison Time Comparison Time Comparison Time * Repeat until conversion ends Comparison Time A/D Conversion Mode Without Sample & Hold Without Sample & Hold With Sample & Hold With Sample & Hold 8 bits 10 bits 8 bits 10 bits Conversion Time Comparison Time Comparison Time End process Sampling Time End process Conversion time at the 1st bit Sampling Time Conversion time at the 2nd bit and the follows 49 φAD 4 φAD 2.0 φAD 2.5 φAD 2.5 φAD 8.0 φAD 59 φAD 4 φAD 2.0 φAD 2.5 φAD 2.5 φAD 8.0 φAD 28 φAD 4 φAD 2.5 φAD 0.0 φAD 2.5 φAD 4.0 φAD 33 φAD 4 φAD 2.5 φAD 0.0 φAD 2.5 φAD 4.0 φAD |
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