M16CSLASH1N datasheet(78/238 Pages) RENESAS

78 / 238 page

Rev.1.00

Oct 20, 2004

page 66 of 222

M16C/1N Group

10. Interrupt

REJ09B0007-0100Z

Set the interrupt priority level to level 0

(Disable interrupt)

Set the polarity select bit

Clear the interrupt request bit to "0"

Set the interrupt priority level to level 1 to 7

(Enable the accepting of interrupt request)

Clear the interrupt enable flag to "0"

(Disable interrupt)

Set the interrupt enable flag to "1"

(Enable interrupt)

10.7 Precautions for Interrupts

10.7.1 Reading Address 0000016

When maskable interrupt is occurred, CPU reads the interrupt information (the interrupt number and

interrupt request level) in the interrupt sequence.

The interrupt request bit of the certain interrupt written in address 0000016 will then be set to "0".

Even if the address 0000016 is read out by software, "0" is set to the enabled highest priority interrupt

source request bit. Therefore, interrupt can be canceled and unexpected interrupt can occur.

Do not read address 0000016 by software.

10.7.2 Setting the Stack Pointer

The value of the stack pointer immediately after reset is initialized to address 000016. Accepting an

interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a

value in the stack pointer before accepting an interrupt. Concerning the first instruction immediately

after reset, generating any interrupts is prohibited.

10.7.3 External Interrupt

________

Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to pins INT0

_______

to INT3 regardless of the CPU operation clock.

________

_______

When changing a polarity of pins INT0 to INT3 and CNTR0, the interrupt request bit may become "1".

Clear the interrupt request bit after changing the polarity. Figure 10.17 shows the switching condition

of external interrupt request.

Figure 10.17 Switching condition of external interrupt request

M16C/1N bảng dữ liệu(PDF) 78 Page - Renesas Technology Corp