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M32C/86 bảng dữ liệu(PDF) 296 Page - Renesas Technology Corp |
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M32C/86 bảng dữ liệu(HTML) 296 Page - Renesas Technology Corp |
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296 / 505 page ![]() Page 273 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 22. Intelligent I/O (Base Timer) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Figure 22.10 Counter Increment Mode FFFF16 800016 Base Timer 000016 The above applies to the following conditions: • The RST1 in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register) • The UD1 and UD0 bits in the G1BCR1 register are set to "002" (counter increment mode) The above applies to the following conditions: • The RST1 in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register) • The UD1 and UD0 bits in the G1BCR1 register are set to "002" (counter increment mode) (2) When the IT bit is set to "1" (bit 14 in the base timer overflows) (1) When the IT bit in the G1BCR0 register is set to "0" (bit 15 in the base timer overflows) "1" "0" "0" "1" Write "0" by program if setting to "0" FFFF16 800016 Base Timer 000016 Bit 14 Overflow Signal BT1R bit in IIO4IR register Bit 15 Overflow Signal BT1R bit in IIO4IR register "1" "0" "0" "1" 400016 C00016 Write "0" by program if setting to "0" |
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