M32CSLASH86 datasheet(295/505 Pages) RENESAS

295 / 505 page

Page 272

22. Intelligent I/O (Base Timer)

)

(

Figure 22.9 Base Timer Block Diagram

Table 22.3 Base Timer Associated Register Settings

(Also applies when using time measurement function, waveform generating function and communication function)

Bit

Function

G1BCR0

BCK1, BCK0

Select count source

DIV4 to DIV0

Select divide ratio of count source

Select the base timer interrupt

G1BCR1

RST2, RST1

Select source for a base timer reset

BTS

Used to start the base timer independently

UD1, UD0

Select how to count

G1POCR0

BTRE

Select source for a base timer reset

G1BT

Read or write base timer value

Set the following registers to set the RST1 bit to "1" (base timer reset by matching the base timer with the G1PO0 register).

G1POCR0

MOD2 to MOD0

Set to "0002" (single-phase waveform output mode)

G1PO0

Set reset cycle

G1FS

FSC0

Set to "0" (waveform generating function)

G1FE

IFE0

Set to "1" (channel operation start)

2(n+1)

Divider

RST1

RST2

Apply "L" to

the INTi Pin

Base Timer

Interrupt Request

BCK1 and BCK0

BTS Bit

Apply the Two-Phase

Pulse Signal

(See the BT1R

bit on Figure

11.14)

Overflow Signal

Base Timer Reset

fBT1

BCK1 and BCK0, IT : Bits in the G1BCR0 register

RST2 to RST0, BTS : Bits in the G1BCR1 register

BTRE : Bit in the G1POCR0 register

BTRE

Base Timer

b14 b15

Matching with

the G1PO0 Register

(i=0,1)

M32C/86 bảng dữ liệu(PDF) 295 Page - Renesas Technology Corp

M32C/86 bảng dữ liệu(HTML) 295 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL