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M32C/86 bảng dữ liệu(PDF) 221 Page - Renesas Technology Corp

tên linh kiện M32C/86
Giải thích chi tiết về linh kiện  RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
PDF  505 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M32C/86 bảng dữ liệu(HTML) 221 Page - Renesas Technology Corp

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Page 198
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17. Serial I/O (Clock Synchronous Serial I/O)
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D0
D1
D2
D3
D4
D5
D6
D7
TxDi
(no inverse)
Transfer clock
"H"
"L"
"H"
"L"
TxDi
(inverse)
"H"
"L"
(1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (not inversed)
Transfer clock
"H"
"L"
(2) When the UiLCH bit in the UiC1 register is set to "1" (inverse)
NOTES:
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on
the falling edge) and the UFORM bit in the UiC0 register is set to "0" (LSB first).
D0
D1
D2
D3
D4
D5
D6
D7
17.1.3 Continuous Receive Mode
When the UiRRM bit in the UiC1 register (i=0 to 4) is set to "1" (continuous receive mode), the TI bit is set
to "0" (data in the UiTB register) by reading the UiRB register. When the UiRRM bit is set to "1", do not set
dummy data in the UiTB register by program.
17.1.4 Serial Data Logic Inverse
When the UiLCH bit (i=0 to 4) in the UiC1 register is set to "1" (inverse), data logic written in the UiTB
register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB
register. Figure 17.13 shows a switching example of the serial data logic.
Figure 17.13 Serial Data Logic Inverse



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