M32CSLASH86 datasheet(217/505 Pages) RENESAS

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Page 194

17. Serial I/O (Clock Synchronous Serial I/O)

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Table 17.2 Register Settings in Clock Synchronous Serial I/O Mode

Bit

Function

UiTB

7 to 0

Set transmit data

UiRB

7 to 0

Received data can be read

OER

Overrun error flag

UiBRG

7 to 0

Set bit rate

UiMR

SMD2 to SMD0

Set to "0012"

CKDIR

Select the internal clock or external clock

IOPOL

Set to "0"

UiC0

CLK1, CLK0

Select count source for the UiBRG register

CRS

_______

Select CTS or RTS when using either

TXEPT

Transmit register empty flag

CRD

_______

Enables or disables the CTS or RTS function

NCH

Select output format of the TxDi pin

CKPOL

Select transmit clock polarity

UFORM

Select either LSB first or MSB first

UiC1

Set to "1" to enable data transmission and reception

Transmit buffer empty flag

Set to "1" to enable data reception

Reception complete flag

UiIRS

Select what causes the UARTi transmit interrupt to be generated

UiRRM

Set to "1" when using continuous receive mode

UiLCH

Set to "1" when using data logic inverse

SCLKSTPB

Set to "0"

UiSMR

7 to 0

Set to "0016"

UiSMR2

7 to 0

Set to "0016"

UiSMR3

2 to 0

Set to "0002"

NODC

Select clock output format

7 to 4

Set to "00002"

UiSMR4

7 to 0

Set to "0016"

i=0 to 4

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