M32CSLASH86 datasheet(162/505 Pages) RENESAS

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Page 139

14. DMACII

)

(

Memory-to-Memory Transfer

/Immediate Data Transfer

Calculation Transfer

Multiple Transfer

Chained Transfer

End-of-Transfer

Interrupt

Not Used

Used

Not Used

Used

Not Used

Used

Not Available

Used

DMAC II

Index

COUNT

MOD

SADR

DADR

COUNT

MOD

SADR

DADR

CADR0

CADR1

COUNT

MOD

SADR

OADR

DADR

IADR0

IADR1

COUNT

MOD

SADR

DADR

IADR0

IADR1

COUNT

MOD

SADR

DADR

CADR0

CADR1

IADR0

IADR1

OADR

8 bytes

12 bytes

COUNT

MOD

SADR

DADR

COUNT

MOD

SADR

DADR

CADR0

CADR1

10 bytes

14 bytes

12 bytes

14 bytes

18 bytes

COUNT

MOD

SADR

DADR

CADR0

CADR1

IADR0

IADR1

16 bytes

COUNT

MOD

SADR1

DADR1

SADRi

DADRi

i=1 to 7

max. 32 bytes

(when i=7)

Transfer Data

Function

(MULT=0)

Function

(MULT=1)

Transfer Mode (MOD)(1)

SIZE

IMM

UPDS

Transfer Unit

Select Bit

UPDD

INTE/

CNT2(2)

Transfer Destination

Direction Select Bit

0: Fixed address

1: Forward address

0: Single transfer

1: Burst transfer

Calculation Transfer

Function Select Bit

0: Not used

1: Used

0: 8 bits

1: 16 bits

BRST/

CNT1(2)

OPER/

CNT0(2)

CHAIN

Transfer Data

Select Bit

Transfer Source

Direction Select Bit

Burst Transfer

Select Bit

End-of-Transfer

Interrupt Select Bit

Chained Transfer

Select Bit

0: Immediate data

1: Memory

Set to "1"

Set to "0"

MULT

(b14 - b8)

Multiple Transfer

Select Bit

0: Multiple

transfer not used

1: Use multiple

transfer

0: Fixed address

1: Forward address

0: Interrupt not used

1: Use interrupt

0: Chained transfer not used

1: Use chained transfer

b6 b5 b4

0 0 0: Do not set

to this value

0 0 1: Once

0 1 0: Twice

1 1 0: 6 times

1 1 1: 7 times

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

Bit Name

Bit

Symbol

NOTES:

1. MOD must be located on the RAM.

2. When the MULT bit is set to "0" (no multiple transfer), bits 6 to 4 becomes the INTE, OPER and BRST

bits. When the MULT bit is set to "1" (multiple transfer), bits 6 to 4 becomes the CNT2 to CNT0 bits.

b15

Table 14.2 DMAC II Index Configuration in Transfer Mode

Figure 14.3 MOD

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