M32CSLASH86 datasheet(156/505 Pages) RENESAS

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Page 133

13. DMAC

)

(

(1) When 8-bit data is transferred

or when 16-bit data is transferred with a 16-bit data bus from an even source address

CPU Clock

Address

Bus

RD Signal

WR Signal

Data Bus

(3) When one wait state is inserted into the source-read bus cycle under the conditions in (1)

(2) When 16-bit data is transferred from an odd source address

or when 16-bit data is transferred and 8-bit bus is used to access a source address

CPU Clock

Address

Bus

RD Signal

WR Signal

Data Bus

CPU Use

Source

Source + 1

(4) When one wait state is inserted into the source-read bus cycle under the conditions in (2)

NOTES:

1. The above applies when the destination-write bus cycle is 2 CPU clock cycles (=1 bus cycle).

However, if the destination-write bus cycle is pleaced under these conditions, it will change to

the same timing as the source-read cycle illustrated above.

Destination

CPU Clock

Address

Bus

RD Signal

WR Signal

Data bus

CPU Use

Source

Destination

CPU Clock

Address

Bus

RD Signal

WR Signal

Data Bus

CPU Use

Source

Source + 1

Destination

CPU Use

Source

Destination

CPU Use

Source

Destination

CPU Clock

Figure 13.6 Transfer Cycle Examples with the Source-Read Bus Cycle

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