M32CSLASH86 datasheet(437/505 Pages) RENESAS

437 / 505 page

Page 414

25. Flash Memory Version

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25.3.8 Full Status Check

If an error occurs when a program or erase operation is completed, the FMR07 and FMR06 bits in the

FMR0 register are set to "1", indicating a specific error. Therefore, execution results can be confirmed by

verifying these bits (full status check).

Table 25.6 lists errors and FMR0 register state. Figure 25.13 shows a flow chart of the full status check

and handling procedure for each error.

Table 25.6 Errors and FMR0 Register State

FMR0 Register

(SRD Register)

State

Error

Error Occurrence Conditions

FMR07

FMR06

(SR5)

(SR4)

Command

• An incorrect command is written

sequence error • A value other than "xxD016" or "xxFF16" is written in the second

bus cycle of the lock bit program, block erase or erase all un-

locked block command(1)

Erase error

• The block erase command is executed on a locked block(2)

• The block erase or erase all unlocked block command is ex-

ecuted on an unlock block, but the erase operation is not suc-

cessfully completed

Program error

• The program command is executed on locked blocks(2)

• The program command is executed on an unlocked block, but the

program operation is not completed as expected

• The lock bit program command is executed but the program op-

eration is not successfully completed

NOTES:

1. The flash memory enters read array mode when command code "xxFF16" is written in the second bus

cycle of these commands. The command code written in the first bus cycle is ignored.

2. When the FMR02 bit is set to "1" (lock bit disabled), no error occurs even under the conditions above.

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