M32CSLASH86 datasheet(361/505 Pages) RENESAS

361 / 505 page

Page 338

23. CAN Module

)

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23.1.16 CANi Mode Register (CiMDR Register) (i=0, 1)

Figure 23.18 C0MDR and C1MDR Registers

23.1.16.1 CMOD Bit

The CMOD bit selects a CAN operating mode.

• Normal operating mode: The CAN module transmits and receives data as expected.

• Bus monitoring mode(1): The CAN module receives data. Output signal from the CANiOUT pin is

fixed as a high-level ("H") signal in bus monitoring mode. The CAN mod

ule transmits neither ACK nor error frame.

• Self-test mode: The CAN module connects the CANiOUT pin to the CANiIN pin internally.

The CAN module can communicate without additional device in loop back mode.

Output signal from the CANiOUT pin is fixed as an "H" signal in self-test mode while

transmitting data. Figure 23.19 shows an image diagram in self-test mode.

NOTES:

1. Do not generate a transmit request in bus monitoring mode.

The CAN module assumes the ACK bit is set to dominant "L" regardless of the ACK bit setting.

Therefore, when the CRC delimiter is received as expected, the CAN module determines the

data is received with no error regardless of the ACK bit setting.

CANi Mode Register (i=0, 1)(1)

Symbol

Address

After Reset(2)

C0MDR

021916

XXXX XX002

C1MDR

029916

XXXX XX002

CMOD

(b7 - b2)

CAN Operating Mode

Select Bit

Bit Name

Function

Bit

Symbol

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

0 0: Normal operating mode

0 1: Bus monitoring mode

1 0: Self-test mode

1 1: Do not set to this value

b1 b0

NOTES:

1. Set the CiMDR register when the STATE_RESET bit in the CiSTR register is set to "1" (CAN module

reset completed).

2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after

reset and supplying the clock to the CAN module.

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