HD6432351 datasheet(300/1025 Pages) RENESAS

300 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 266 of 988

REJ09B0330-0300

Full Address Mode (Burst Mode)

Figure 7.21 shows a transfer example in which

TEND output is enabled and word-size full address

mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16-

bit, 2-state access space.

DMA

read

Address bus

LWR

TEND

HWR

Bus release

DMA

write

DMA

dead

DMA

read

DMA

write

DMA

read

DMA

write

Bus release

Burst transfer

Last transfer cycle

Figure 7.21 Example of Full Address Mode (Burst Mode) Transfer

In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends.

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead

cycle is inserted after the DMA write cycle.

If a request from another higher-priority channel is generated after burst transfer starts, that

channel has to wait until the burst transfer ends.

If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state,

the DTME bit is cleared and the channel is placed in the transfer disabled state. If burst transfer

has already been activated inside the DMAC, the bus is released on completion of a one-byte or

one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer

cycle of the burst transfer has already been activated inside the DMAC, execution continues to the

end of the transfer even if the DTME bit is cleared.

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