HD6432351 datasheet(298/1025 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 264 of 988

REJ09B0330-0300

7.5.10

DMAC Bus Cycles (Dual Address Mode)

Short Address Mode

Figure 7.19 shows a transfer example in which

TEND output is enabled and byte-size short

address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state

access space to internal I/O space.

DMA

read

Address bus

LWR

TEND

HWR

Bus release

Last transfer

cycle

DMA

write

DMA

dead

DMA

read

DMA

write

DMA

read

DMA

write

Bus release

Bus

release

Bus

release

Figure 7.19 Example of Short Address Mode Transfer

A one-byte or one-word transfer is performed for one transfer request, and after the transfer the

bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC.

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead

cycle is inserted after the DMA write cycle.

In repeat mode, when

TEND output is enabled, TEND output goes low in the transfer cycle in

which the transfer counter reaches 0.

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