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HD6432351 bảng dữ liệu(HTML) 297 Page - Renesas Technology Corp |
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297 / 1025 page  Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 263 of 988 REJ09B0330-0300 7.5.9 Basic DMAC Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.18. In this example, word- size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings. φ Address bus DMAC cycle (1-word transfer) RD LWR HWR Source address Destination address CPU cycle CPU cycle T1 T2 T3 T1 T2 T3 T1 T2 Figure 7.18 Example of DMA Transfer Bus Timing The address is not output to the external address bus in an access to on-chip memory or an internal I/O register. |
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