HD6432351 datasheet(271/1025 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 237 of 988

REJ09B0330-0300

Figure 7.3 illustrates operation in sequential mode.

Address T

Address B

Transfer

IOAR

1 byte or word transfer performed in

response to 1 transfer request

Notes:

Address T = L

Address B = L + (–1)DTID • (2DTSZ • (N–1))

Where : L = Value set in MAR

N = Value set in ETCR

Figure 7.3 Operation in Sequential Mode

The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a

transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends.

If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC.

The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.

Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external

requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5

compare match/input capture A interrupts. External requests can be set for channel B only.

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