HD6432351 datasheet(269/1025 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 235 of 988

REJ09B0330-0300

(5) Normal mode

Auto-request: By means of register settings only, the DMAC is activated, and transfer continues

until the specified number of transfers have been completed. An interrupt request can be sent to

the CPU or DTC when transfer is completed. Both addresses are specified as 24 bits.

• Cycle steal mode: The bus is released to another bus master every byte or word transfer.

• Burst mode: The bus is held and transfer continued until the specified number of transfers have

been completed.

External request: In response to a single transfer request, the specified number of transfers are

carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC

when the specified number of transfers have been completed. Both addresses are specified as 24

bits.

(6) Block transfer mode

In response to a single transfer request, a block transfer of the specified block size is carried out.

This is repeated the specified number of times, once each time there is a transfer request. At the

end of each single block transfer, one address is restored to its original setting. An interrupt

request can be sent to the CPU or DTC when the specified number of block transfers have been

completed. Both addresses are specified as 24 bits.

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