H838532H datasheet(320/508 Pages) RENESAS

320 / 508 page

Section 10 Serial Communication Interface

Rev. 1.00 May 30, 2008 Page 300 of 484

REJ09B0436-0100

Bit 6: Receive data register full (RDRF)

Bit 6 indicates that received data is stored in RDR.

Bit 6

RDRF

Description

There is no receive data in RDR

(initial value)

Clearing conditions:

After reading RDRF = 1, cleared by writing 0 to RDRF

When RDR data is read by an instruction

There is receive data in RDR

Setting condition:

When reception ends normally and receive data is transferred from RSR to RDR

Note:

If an error is detected in the receive data, or if the RE bit in SCR3 has been cleared to 0,

RDR and bit RDRF are not affected and retain their previous state.

Note that if data reception is completed while bit RDRF is still set to 1, an overrun error

(OER) will result and the receive data will be lost.

Bit 5: Overrun error (OER)

Bit 5 indicates that an overrun error has occurred during reception.

Bit 5

OER

Description

Reception in progress or completed*

(initial value)

Clearing condition:

After reading OER = 1, cleared by writing 0 to OER

An overrun error has occurred during reception*

Setting condition:

When reception is completed with RDRF set to 1

Notes: 1. When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous

state.

2. RDR retains the receive data it held before the overrun error occurred, and data

received after the error is lost. Reception cannot be continued with bit OER set to 1,

and in synchronous mode, transmission cannot be continued either.

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