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H838532H bảng dữ liệu(PDF) 290 Page - Renesas Technology Corp |
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H838532H bảng dữ liệu(HTML) 290 Page - Renesas Technology Corp |
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290 / 508 page ![]() Section 9 Timers Rev. 1.00 May 30, 2008 Page 270 of 484 REJ09B0436-0100 Bit 2: Watchdog timer module standby mode control (WDCKSTP) Bit 2 controls setting and clearing of module standby mode for the watchdog timer. WDCKSTP Description 0 Watchdog timer is set to module standby mode 1 Watchdog timer module standby mode is cleared (initial value) Note: WDCKSTP is valid when the WDON bit is cleared to 0 in timer control/status register W (TCSRW). If WDCKSTP is set to 0 while WDON is set to 1 (during watchdog timer operation), 0 will be set in WDCKSTP but the watchdog timer will continue its watchdog function and will not enter module standby mode. When the watchdog function ends and WDON is cleared to 0 by software, the WDCKSTP setting will become valid and the watchdog timer will enter module standby mode. (4) Port Mode Register 3 (PMR3) Bit Initial value Read/Write 7 AEVL 0 R/W 6 AEVH 0 R/W 5 WDCKS 0 R/W 4 NCS 0 R/W 3 IRQ0 0 R/W 0 PWM 0 R/W 2 — 1 — 1 UD 0 R/W PMR3 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 3 pins. Only the bit relating to the watchdog timer is described here. For details of the other bits, see section 8, I/O Ports. Bit 5: Watchdog timer source clock select (WDCKS) WDCKS Description 0 φ/8192 selected (initial value) 1 φw/32 selected |
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