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H838532H bảng dữ liệu(PDF) 289 Page - Renesas Technology Corp |
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H838532H bảng dữ liệu(HTML) 289 Page - Renesas Technology Corp |
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289 / 508 page ![]() Section 9 Timers Rev. 1.00 May 30, 2008 Page 269 of 484 REJ09B0436-0100 Bit 0 WRST Description 0 Clearing condition: Reset by RES pin When TCSRWE = 1, and 0 is written in both B0WI and WRST 1 Setting condition: When TCW overflows and an internal reset signal is generated (2) Timer Counter W (TCW) Bit Initial value Read/Write 7 TCW7 0 R/W 6 TCW6 0 R/W 5 TCW5 0 R/W 4 TCW4 0 R/W 3 TCW3 0 R/W 0 TCW0 0 R/W 2 TCW2 0 R/W 1 TCW1 0 R/W TCW is an 8-bit read/write up-counter, which is incremented by internal clock input. The input clock is φ/8192 or φw/32. The TCW value can always be written or read by the CPU. When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to 1 in TCSRW. Upon reset, TCW is initialized to H'00. (3) Clock Stop Register 2 (CKSTPR2) — WDCKSTP PWCKSTP LDCKSTP — — — AECKSTP 7 6 543210 1 1111111 — R/W R/W R/W ——— R/W Bit Initial value Read/Write CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the watchdog timer is described here. For details of the other bits, see the sections on the relevant modules. |
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