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H838532H bảng dữ liệu(PDF) 242 Page - Renesas Technology Corp |
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H838532H bảng dữ liệu(HTML) 242 Page - Renesas Technology Corp |
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242 / 508 page ![]() Section 9 Timers Rev. 1.00 May 30, 2008 Page 222 of 484 REJ09B0436-0100 9.3.4 Timer C Operation States Table 9.7 summarizes the timer C operation states. Table 9.7 Timer C Operation States Operation Mode Reset Active Sleep Watch Sub- active Sub-sleep Standby Module Standby TCC Interval Reset Functions Functions Halted Functions/ Halted* Functions/ Halted* Halted Halted Auto reload Reset Functions Functions Halted Functions/ Halted* Functions/ Halted* Halted Halted TMC Reset Functions Retained Retained Functions Retained Retained Retained Note: * When φw/4 is selected as the TCC internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. This results in a maximum count cycle error of 1/ φ (s). When the counter is operated in subactive mode or subsleep mode, either select φw/4 as the internal clock or select an external clock. The counter will not operate on any other internal clock. If φw/4 is selected as the internal clock for the counter when φw/8 has been selected as subclock φ SUB, the lower 2 bits of the counter operate on the same cycle, and the operation of the least significant bit is unrelated to the operation of the counter. |
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