H838532H datasheet(240/508 Pages) RENESAS

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Section 9 Timers

Rev. 1.00 May 30, 2008 Page 220 of 484

REJ09B0436-0100

(4) Clock Stop Register 1 (CKSTPR1)

—

TFCKSTP TCCKSTP TACKSTP

S31CKSTP S32CKSTP ADCKSTP TGCKSTP

543210

1111111

R/W

Bit

Initial value

Read/Write

CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral

modules. Only the bit relating to timer C is described here. For details of the other bits, see the

sections on the relevant modules.

Bit 1: Timer C module standby mode control (TCCKSTP)

Bit 1 controls setting and clearing of module standby mode for timer C.

TCCKSTP

Description

Timer C is set to module standby mode

Timer C module standby mode is cleared

(initial value)

9.3.3

Timer Operation

(1) Interval Timer Operation

When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit

interval timer.

Upon reset, TCC is initialized to H'00 and TMC to H'18, so TCC continues up-counting as an

interval up-counter without halting immediately after a reset. The timer C operating clock is

selected from seven internal clock signals output by prescalers S and W, or an external clock input

at pin TMIC. The selection is made by bits TMC2 to TMC0 in TMC.

TCC up/down-count control can be performed either by software or hardware. The selection is

made by bits TMC6 and TMC5 in TMC.

After the count value in TCC reaches H'FF (H'00), the next clock input causes timer C to overflow

(underflow), setting bit IRRTC to 1 in IRR2. If IENTC = 1 in interrupt enable register 2 (IENR2),

a CPU interrupt is requested.

At overflow (underflow), TCC returns to H'00 (H'FF) and starts counting up (down) again.

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