SH7261 datasheet(152/1348 Pages) RENESAS

152 / 1348 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 Sep. 07, 2007 Page 120 of 1312

REJ09B0320-0200

UBC

H-UDI

ADC

ROM-DEC

MTU2

RTC

WDT

IIC3

DMAC

SCIF

RCAN-ET

IEB

SSI

TMR

UBC:

User break controller

H-UDI:

User debugging interface

ADC:

A/D converter

ROM-DEC: CD-ROM decoder

MTU2:

Multi-function timer pulse unit 2

RTC:

Realtime clock

WDT:

Watchdog timer

IIC3:

I2C bus interface 3

DMAC:

Direct memory access controller

SCIF:

Serial communication interface with FIFO

RCAN-ET: Controller area network

IEB:

IEBusTM controller

SSI:

Serial sound interface

TMR:

ICR0:

ICR1:

ICR2:

IRQRR:

PINTER:

PIRR:

IBCR:

IBNR:

IPR01, IPR02, IPR05 to IPR16:

8-bit timer

Interrupt control register 0

Interrupt control register 1

Interrupt control register 2

IRQ interrupt request register

PINT interrupt enable register

PINT interrupt request register

Bank control register

Bank number register

Interrupt priority registers 01, 02, 05 to 16

CPU

I3 I2 I1 I0

(Interrupt request)

PINTER

IBCR

IPR01, IPR02,

IPR05 to IPR16

[Legend]

ICR0

ICR2

PIRR

IBNR

ICR1

IRQRR

PINT7 to PINT0

IRQ7 to IRQ0

NMI

IPR

Input control

INTC

Priority

identifier

Com-

parator

Interrupt

request

Module bus

Bus

interface

Figure 6.1 Block Diagram of INTC

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