SH7261 datasheet(146/1348 Pages) RENESAS

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Section 5 Exception Handling

Rev. 2.00 Sep. 07, 2007 Page 114 of 1312

REJ09B0320-0200

The FPU exception flag field (Flag) of FPSCR is always updated regardless of whether or not an

FPU exception has been accepted, and remains set until explicitly cleared by the user through an

instruction. The FPU exception source field (Cause) of FPSCR changes each time an FPU

instruction is executed.

When the V bit in the FPU exception enable field (Enable) of FPSCR is set and the QIS bit in

FPSCR is also set, FPU exception is generated when qNAN or

±∞ is input to a floating point

operation instruction source.

5.8

When Exception Sources Are Not Accepted

When an address error, bus error, FPU exception, register bank error (overflow), or interrupt is

generated immediately after a delayed branch instruction, it is sometimes not accepted

immediately but stored instead, as shown in table 5.11. When this happens, it will be accepted

when an instruction that can accept the exception is decoded.

Table 5.11

Exception Source Generation Immediately after Delayed Branch Instruction

Exception Source

Point of Occurrence

Address

Error

Bus Error

FPU

Exception

Bank Error

(Overflow)

Interrupt

Immediately after a

delayed branch

instruction*

Not accepted

Not accepted Not accepted Not accepted Not accepted

Note:

Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF.

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