SH7261 datasheet(126/1348 Pages) RENESAS

126 / 1348 page

Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 Sep. 07, 2007 Page 94 of 1312

REJ09B0320-0200

4.6.4

Note on Using a PLL Oscillation Circuit

In the PLLVcc and PLLVss connection pattern for the PLL, signal lines from the board power

supply pins must be as short as possible and pattern width must be as wide as possible to reduce

inductive interference.

In clock operating mode 3, the EXTAL pin is pulled up and the XTAL pin is left open.

Since the analog power supply pins of the PLL are sensitive to the noise, the system may

malfunction due to inductive interference at the other power supply pins. To prevent such

malfunction, the analog power supply pin Vcc and the digital power supply pins VccR and PVcc

should not supply the same resources on the board if at all possible.

PLLVcc

PLLVss

Vcc

Vss

Power supply

Signal lines prohibited

Figure 4.4 Note on Using PLL Oscillation Circuit

4.6.5

Note on Changing the Multiplication Rate

If the multiplication rate is changed by the frequency control register (FRQCR) during transfer by

the DMAC, the DMAC stops its operation without waiting for the completion of the transfer.

Thus, the DMA transfer is not guaranteed. Therefore, when changing the multiplication rate with

the frequency control register (FRQCR), wait for the completion of the DMA transfer or stop the

DMA transfer to change the setting of the frequency control register (FRQCR).

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