R8C datasheet(153/199 Pages) RENESAS

153 / 199 page

R8C/10 Group

Rev.1.20 Jan 27, 2006

page 143 of 180

REJ09B0019-0120

17.4 CPU Rewrite Mode

In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the

CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-

board without having to use a ROM programmer, etc. Make sure the Program and the Block Erase

commands are executed only on each block in the user ROM area.

For interrupts requested during an erase operation in CPU rewrite mode, the R8C/10 flash module offers

an `erase-suspend` feature which allow the erase operation to be suspended, and access made avail-

able to the flash.

During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or

Erase Write 1 (EW1) mode. Table 17.3 lists the differences between Erase Write 0 (EW0) and Erase

Write 1 (EW1) modes.

Table 17.3 EW0 Mode and EW1 Mode

Item

EW0 mode

EW1 mode

Operation mode

Single chip mode

Areas in which a

User ROM area

rewrite control

program can be located

Areas in which a

Must be transferred to any area other Can be executed directly in the user

rewrite control

than the flash memory (e.g., RAM)

ROM area

program can be executed before being executed

Areas which can be

User ROM area

rewritten

However, this does not include the

block in which a rewrite control program

exists(1)

Software command

None

• Program, Block Erase command

limitations

Cannot be executed on any block in

which a rewrite control program exists

• Read Status Register command

Cannot be executed

Modes after Program or

Read Status Register mode

Read Array mode

Erase

CPU status during Auto

Operating

Hold state (I/O ports retain the state in

Write and Auto Erase

which they were before the command

was executed)

Flash memory status

• Read the FMR0 register FMR00,

Read the FMR0 register FMR00,

detection

FMR06, and FMR07 bits in a

FMR06, and FMR07 bits in a program

program

• Execute the Read Status Register

command to read the status

Conditions for

Set the FMR40 and FMR41 bits in

When an interrupt which is set for

transferring to

the FMR4 register to “1” by program. enabled occurs while the FMR40 bit in

erase-suspend

the FMR4 register is set to “1”.

NOTES:

1. Block 1 and Block 0 are enabled for rewrite by setting the FMR02 bit in the FMR0 register to “1” (rewrite

enabled).

17.4 CPU Rewrite Mode

R8C bảng dữ liệu(PDF) 153 Page - Renesas Technology Corp

R8C bảng dữ liệu(HTML) 153 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL