R8C datasheet(54/199 Pages) RENESAS

54 / 199 page

R8C/10 Group

Rev.1.20 Jan 27, 2006

page 44 of 180

REJ09B0019-0120

• Interrupt Priority

If two or more interrupt requests are generated while executing one instruction, the interrupt request

that has the highest priority is accepted.

For maskable interrupts (peripheral functions), any desired priority level can be selected using the

ILVL2 to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their

interrupt priority is resolved by hardware, with the highest priority interrupt accepted.

The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 10.8

shows the Hardware Interrupt Priority.

Software interrupts are not affected by the interrupt priority. If an instruction is executed, control

branches invariably to the interrupt routine.

• Returning from an Interrupt Routine

The FLG register and PC in the state in which they were immediately before entering the interrupt

sequence are restored from the stack by executing the REIT instruction at the end of the interrupt

routine. Thereafter the CPU returns to the program which was being executed before accepting the

interrupt request.

Return the other registers saved by a program within the interrupt routine using the POPM or similar

instruction before executing the REIT instruction.

Figure 10.8 Hardware Interrupt Priority

Reset > WDT/Oscillation stop detection > Peripheral function > Single step > Address match

10.1 Interrupt Overview

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