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M5M5V216ART bảng dữ liệu(PDF) 3 Page - Renesas Technology Corp |
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M5M5V216ART bảng dữ liệu(HTML) 3 Page - Renesas Technology Corp |
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3 / 9 page ![]() M5M5V216ATP,RT revision-03, 14.Jan.'03 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM MITSUBISHI LSIs FUNCTION TABLE 2 FUNCTION The M5M5V216ATP,RT is organized as 131,072-words by 16-bit. These dev ices operate on a single +2.7~3.6V power supply, and are directly TTL compatible to both input and output. Its f ully st atic circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of the dev ice control inputs BC1 , BC2 , S , W and OE. Each mode is summarized in the f unction table. A write operation is executed whenev er the low lev el W ov erlaps with the low lev el BC1 and/or BC2 and the low lev el S. The address(A0~A16) must be set up bef ore the write cyc le and must be stable during the entire cyc le. A read operation is executed by s etting W at a high lev el and OE at a low lev el while BC1 and/or BC2 and S are in an activ e state(S=L). When setting BC1 at the high lev el and other pins are in an activ e stage , upper-by te are in a selesctable mode in which both reading and writing are enabled, and lower-byte are in a non-selectable mode. And when setting BC2 at a high lev el and other pins are in an activ e stage, lower- byt e are in a selectable mode and upper-by te are in a non-selectable mode. When setting BC1 and BC2 at a high lev el or S at a high lev el, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and S. The power supply c urrent is reduced as low as 0.3µA(25 C, ty pical), and the memory data can be held at +2V power supply, enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode. BLOCK DIAGRAM Mode S W H X X High-Z S BC1 BC2 OE DQ1~8 X X Non selection DQ9~16 Icc High-Z Standby High-Z High-Z L X L L H Din High-Z Active L H L H Read High-Z Dout Active L L H L Active L H L Active L L High-Z High-Z Active H L H H High-Z L L Dout H L L Read Dout Active L L Din L L X Write Din Active H High-Z H H High-Z High-Z Non selection H H X X Standby Write L H L L Write Din Active X L L H Read High-Z Active L Dout H High-Z MEMORY ARRAY 131072 WORDS x 16 BITS CLOCK GENERATOR A0 A1 A15 A16 S BC1 BC2 W OE DQ 8 DQ 1 DQ 16 DQ 9 - Vcc GND L Note : "H" and "L" in this table mean VIH or VIL. "X" in this table should be "H" or "L". |
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