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M66596FP bảng dữ liệu(PDF) 105 Page - Renesas Technology Corp

tên linh kiện M66596FP
Giải thích chi tiết về linh kiện  ASSP (USB2.0 Dual Function Controller)
PDF  131 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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M66596FP bảng dữ liệu(HTML) 105 Page - Renesas Technology Corp

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M66596FP/WG
rev .1.00
2006.3.14
page 105 of 127
4.8 Required timing conditions (VIF = 2.7~3.6V, or 1.6~2.0V)
Rated value
Symbol
Item
Measurement
conditions /
other
Min.
Typ.
Max.
Unit
Ref.
no.
tsuw (A)
Address write setup time
CL=50 pF
30
ns
30
tsur (A)
Address read setup time
0
ns
31
tsu (A - ALE)
Address setup time when using multiplex
bus
10
ns
32
thw (A)
Address write hold time
0
ns
33
thr (A)
Address read hold time
30
ns
34
th (A - ALE)
Address setup hold time when using
multiplex bus
0
ns
35
tw (ALE)
ALE pulse width when using multiplex bus
10
ns
36
tdwr (ALE - CTRL)
Write / read delay time when using multiplex
bus
7
ns
37
trec (ALE)
ALE recovery time when using multiplex bus
0
ns
38
tw (CTRL)
Control pulse width (write)
30
ns
39
trec (CTRL)
Control recovery time (FIFO)
30
ns
40
trecr (CTRL)
Control recovery time (REG)
12
ns
41
twr (CTRL)
Control pulse width (read)
30
ns
42
tsu (D)
Data setup time
20
ns
43
th (D)
Data hold time
0
ns
44
tsu (Dend)
DEND input setup time
30
ns
45
th (Dend)
DEND input hold time
0
ns
46
8-bit FIFO access
30
ns
16-bit FIFO access
50
ns
tw (cycle)
FIFO access
cycle time
8- / a6-bit FIFO access
when using multiplex bus
84
ns
47
When using split bus, and
Obus=0
12
ns
When using split bus, and
Obus=1
*1)
30
ns
tw (CTRL_B)
Control pulse
width when
using burst
transfers
When using DMA transfers
with CPU bus
30
ns
48
trec (CTRL_B)
Control recovery time for burst transfers
12
ns
49
tsud (A)
DMA address write setup time
15
ns
50
thd (A)
DMA address write hold time
0
ns
51
tw (RST)
Reset pulse width time
100
ns
52
tst (RST)
Control starts time after reset
500
ns
53
Key
tsuw: Write setup time, tsur: Read setup time, tsu: Setup time
thw: Write hold time, thr: Read hold time, th: Hold time, tw: Pulse width, twr: Read pulse width
tdwr: Read / write delay time, trec: Recovery time, trecr: Register recovery time
tsud: DMA setup time, thd: DMA hold time, tst: Start time
(A): Address, (D): Data, (CTRL): Control, (CTRL_B): Burst control, (ALE): ALE
*1) Only for data writing, when the DACK0_N signal is assuring an active period of at least 30 ns, the DSTB0_N
signal can be accessed at a minimum of 12 ns.



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