M66596FP datasheet(56/131 Pages) RENESAS

56 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 56 of 127

3.1.8

State transition timing

3.1.8.1 Starting the internal clock supply (from the H/W reset state to the normal operating state)

Figure 3.5 shows a diagram of the clock supply start control timing of the controller. The transition from the H/W

reset state to the normal operating state should be done through operation of the bits at the timing noted below.

(1)

Software enables the oscillation buffer.

"XCKE=1"

(2)

Software waits for oscillation to stabilize.

(The oscillation stabilization time varies depending

on the oscillator.)

(3)

Software enables the reference clock suppliance

"RCKE=1", "PLLC=1"

and the PLL operation

(4)

Software waits for the PLL to lock.

(A waiting time of at least 8.3 us is necessary.)

(5)

Software enables the internal clock suppliance. "SCKE=1"

XCKE

RCKE

PLLC

SCKE

(2)

Approximately 1.5 ms

(varies depending on oscillation probe)

PCUT

(4)

min 8.3us

(1)

(3)

(5)

Start of internal

clock supply

procedure

Figure 3.5 Clock supply start control timing

3.1.8.2 Stopping the internal clock supply (from the normal operating state to the low-power sleep state)

Figure 3.6 shows a diagram of the low-power control timing from the normal operating state to the low-power sleep

state. The transition from the normal operating state to the low-power sleep state should be done through operation

of the bits at the timing noted below.

(1)

Software disables the internal clock suppliance."SCKE=0"

(2)

Software waits until the internal clock stops.

(A waiting time of at least 300 ns is necessary.)

(3)

Software disables the PLL.

"PLLC=0"

(4)

Software waits for the PLL to stop.

(A waiting time of at least 300 ns is necessary.)

(5)

Software disables reference clock suppliance.

"RCKE=0"

(6)

Software waits until the reference clock stops. (A waiting time of at least 300 ns is necessary.)

(7)

Software sets the bit for low-power sleep state. "PCUT=1"

(8)

The controller disables the oscillation buffer.

"XCKE=0(H/W)" *1)

*1) The software must not set the XCKE bit to "0".

XCKE(H/W)

RCKE

PLLC

SCKE

PCUT

(2) min 300ns

(1)

Start of transit to

the low power

state

(3)

(5)

(7)

(4) min 300ns

(6) min 300ns

(8)

Figure 3.6 Transition control timing to the low-power sleep state

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