M66596FP datasheet(60/131 Pages) RENESAS

60 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 60 of 127

3.2 Interrupt functions

3.2.1

An overview of interrupt functions

Table 3.7 shows the interrupt functions of the controller.

Table 3.7 Interrupt functions

Bit

Interrupt name

Cause of interrupt

Mode

status

Note

VBINT

VBUS interrupt

When a change in the state of the VBUS input pin has

been detected (change in both edge, ”L”

→”H”, ”H” →”L”)

Host,

Peripheral

VBSTS

3.2.9

RESM

Resume interrupt

When a change in the state of the USB bus has been

detected in the suspended state

(J-State

→K-State or J-State→SE0)

Peripheral

3.2.10

SOFR

Frame No.

Refresh interrupt

When an SOF packet with a different frame number

has been transmited

When “SOFRM=0” :

When an SOF packet with a different frame number

When “SOFRM=1” :

When the controller detects a corruption of an SOF

packet

Host,

Peripheral

3.2.8

DVST

Device State

Transition interrupt

When a device state transition has been detected

USB bus reset detected

Suspend state detected

Set Address request received

Set Configuration request received

Peripheral

DVSQ

3.2.6

CTRT

Control Transfer

Stage Transition

interrupt

When a stage transition has been detected in a control

transmission

Setup stage completed

Control write transfer status stage transition

Control read transfer status stage transition

Control transfer completed

Control transfer sequence error occurred

Peripheral

CTSQ

3.2.7

BEMP

Buffer Empty

interrupt

When transmission of all of the data in the buffer

memory has been completed

When an excessive maximum packet size error has

been detected

Host,

Peripheral

PIPEBE

3.2.5

NRDY

Buffer Not Ready

interrupt

When a STALL token received from a peripheral.

When the response from abc is unreceivable(Pachet

ignore).

When an IN token has been received and there is no

data that can be sent to the buffer memory

When an OUT token has been received and there is

no area in which data can be stored in the buffer

memory, so reception is not possible

When a CRC error or bit stuffing error occurred in

isochronous transfer

Host,

Peripheral

PIPEN

RDY

3.2.4

BRDY

Buffer Ready

interrupt

When the buffer is ready (reading or writing is enabled)

Host,

Peripheral

PIPEB

RDY

3.2.3

BCHG

USB bus change

interrupt

When a USB bus state changes. Please do not enable

interruption during communication (at the time of

"UACT=1" setup). The bus change interruption is

generated whichever it has chosen of Host and

Peripheral mode.

Host,

Peripheral

3.2.11

SACK

Setup Transaction

complete

When the ACK packet from peripheral device is received

at the time of sending setup transaction at Host mode.

Host

3.2.13

SIGN

Setup Transaction

Error detect

When the ACK packet from peripheral device is not

received at the time of sending setup transaction at Host

mode.

Host

3.2.14

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