4513 datasheet(24/97 Pages) RENESAS

24 / 97 page

4513/4514 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

(7) Interrupt sequence

Interrupts only occur when the respective INTE flag, interrupt en-

able bits (V10–V13 and V20–V23), and interrupt request flag are

“1.” The interrupt actually occurs 2 to 3 machine cycles after the

cycle in which all three conditions are satisfied. The interrupt oc-

curs after 3 machine cycles only when the three interrupt condi-

tions are satisfied on execution of other than one-cycle instructions

(Refer to Figure 16).

Fig. 16 Interrupt sequence

System clock

EXF0, EXF1

T1F, T2F, T3F,

T4F, ADF,SIOF

INT0, INT1

2 to 3 machine cycles

(Notes 2, 3)

The program starts from

the interrupt address.

Flag cleared

Interrupt enabled state

When an interrupt request flag is set after its interrupt is enabled (Note 1)

1 machine cycle

EI instruction

execution cycle

Interrupt enable

flag (INTE)

Retaining level of system

clock for 4 periods or more

is necessary.

Interrupt disabled state

External

interrupt

Timer 1,

Timer 2,

Timer 3,

Timer 4,

A-D, and

Serial I/O

interrupts

Interrupt activated

condition is satisfied.

2: The address is stacked to the last cycle.

3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.

Notes 1: The 4513/4514 Group operates in the middle-speed mode after system is released from reset.

f (XIN) (middle-speed mode)

f (XIN) (high-speed mode)

4513 bảng dữ liệu(PDF) 24 Page - Renesas Technology Corp

4513 bảng dữ liệu(HTML) 24 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

bảng dữ liệu tải về

Link URL