4513 datasheet(83/97 Pages) RENESAS

83 / 97 page

4513/4514 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

V13

V12

V11

V10

V23

V22

V21

V20

Serial I/O interrupt enable bit

A-D interrupt enable bit

Timer 4 interrupt enable bit

Timer 3 interrupt enable bit

Interrupt control register V1

Timer 2 interrupt enable bit

Timer 1 interrupt enable bit

External 1 interrupt enable bit

External 0 interrupt enable bit

Interrupt disabled (SNZT2 instruction is valid)

Interrupt enabled (SNZT2 instruction is invalid)

Interrupt disabled (SNZT1 instruction is valid)

Interrupt enabled (SNZT1 instruction is invalid)

Interrupt disabled (SNZ1 instruction is valid)

Interrupt enabled (SNZ1 instruction is invalid)

Interrupt disabled (SNZ0 instruction is valid)

Interrupt enabled (SNZ0 instruction is invalid)

Interrupt disabled (SNZSI instruction is valid)

Interrupt enabled (SNZSI instruction is invalid)

Interrupt disabled (SNZAD instruction is valid)

Interrupt enabled (SNZAD instruction is invalid)

Interrupt disabled (SNZT4 instruction is valid)

Interrupt enabled (SNZT4 instruction is invalid)

Interrupt disabled (SNZT3 instruction is valid)

Interrupt enabled (SNZT3 instruction is invalid)

R/W

at RAM back-up : 00002

at reset : 00002

R/W

at RAM back-up : 00002

at reset : 00002

Interrupt control register V2

R/W

at RAM back-up : 00002

at reset : 00002

CONTROL REGISTERS

I13

I12

I11

I10

I23

I22

I21

I20

Not used

Interrupt valid waveform for INT0 pin/

return level selection bit (Note 2)

INT0 pin edge detection circuit control bit

INT0 pin

timer 1 control enable bit

This bit has no function, but read/write is enabled.

Falling waveform (“L” level of INT1 pin is recognized with the SNZI1

instruction)/“L” level

Rising waveform (“H” level of INT1 pin is recognized with the SNZI1

instruction)/“H” level

One-sided edge detected

Both edges detected

Disabled

Enabled

Not used

Interrupt valid waveform for INT1 pin/

return level selection bit (Note 3)

INT1 pin edge detection circuit control bit

INT1 pin

timer 3 control enable bit

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.

3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.

Interrupt control register I1

R/W

at RAM back-up : state retained

at reset : 00002

This bit has no function, but read/write is enabled.

Falling waveform (“L” level of INT0 pin is recognized with the SNZI0

instruction)/“L” level

Rising waveform (“H” level of INT0 pin is recognized with the SNZI0

instruction)/“H” level

One-sided edge detected

Both edges detected

Disabled

Enabled

Interrupt control register I2

R/W

at RAM back-up : state retained

at reset : 00002

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